DM {P1} g. 22 a. latency: Lsend_msg + Lreq_msg + Lread_memory + Ldata_msg + Lrcv_data = 6 + 15 + 100 + 30 + 15 = 166 b.

120: (DS, {P0,P15}, 00 20) e. 120: (DS, {P0,P1,P15}, 00 20) f. 120: (DM, {P1}, 00 20) g. 120: (DS, {P0,P1}, 00 20) h. 120: (DM, {P1}, 00 20) Memory is not updated on a write to a block that is M in another cache. 17 a. P0: write 100 <-- 80 No messages, hits in P0’s cache b. P0: write 108 <-- 88 Send invalidate to P15 c. P0: write 118 <-- 90 Send invalidate to P1 d. 32. 31 Cache states. 32 Directory states. 19 The Exclusive state (E) combines properties of Modified (M) and Shared (S). The E state allows silent upgrades to M, allowing the processor to write the block without communicating this fact to memory.

36. 36 Results from running Skippy on Disk Beta. The minimal transfer time determines the y-axis value of point 3 (P3). The minimal transfer time divided by the rotational latency determines the x-axis value of point 3, as it reflects the number of sectors traversed in that time. The slope of the lines L1 . . L4 is determined by dividing the rotational time by the number of sectors per track; L2 is the base line and essentially goes through the y-axis at x = 0, L3 is just a head switch time above L2, and L4 a cylinder switch time above L2.

### A solution manual to Computer Architecture: A Quantitative Approach 4E (John L. Hennessy & David Patterson) by John L. Hennessy & David Patterson

by Ronald

4.3